Analog Mixed Signal
The confluence of the analog and digital universes lays the basis for AMS design.
The cross domain understanding of our experts makes this critical point of interface efficient and error free.
- Requirement & Feasibility Analysis
- Modeling & Mixed Signal Verification
- Circuit Design, Simulation & Analysis
- Block & Full chip Layout
- Physical verification / DRC, LVS
- Parasitic Extraction & Post Layout Simulation
- GDSII sign-off
- Silicon Evaluation
Circuit Design
- Domain focus: Power Management, Data Converters, Clock Circuits, General Purpose IO libraries
- Full chip integration and Test chips development
- IP development & feature enhancements
Analog/ Mixed Signal Layout
- Domain focus: Power Management,HPA/ RF, IO & High Speed Layouts
- Layout Automation through Perl, Shell, Tcl scripting
- Exposure to 14/ 16/ 22 nm FinFET, 28-180 nm CMOS technology nodes
- Layout migration across fabs & nodes
Modeling & Verification
- Performance & functional modeling through Verilog A, Verilog AMS & Verilog
- Full chip verification: Mixed signal, mixed mode and module level verification for Power managements chips & Audio codec system
- SV-UVM based mixed signal verification
Circuit Design
- Domain focus: Power Management, Data Converters, Clock Circuits, General Purpose IO libraries
- Full chip integration and Test chips development
- IP development & feature enhancements
Analog/ Mixed Signal Layout
- Domain focus: Power Management,HPA/ RF, IO & High Speed Layouts
- Layout Automation through Perl, Shell, Tcl scripting
- Exposure to 14/ 16/ 22 nm FinFET, 28-180 nm CMOS technology nodes
- Layout migration across fabs & nodes
Modeling & Verification
- Performance & functional modeling through Verilog A, Verilog AMS & Verilog
- Full chip verification: Mixed signal, mixed mode and module level verification for Power managements chips & Audio codec system
- SV-UVM based mixed signal verification
