Believing in excellence through diversity, cosmopolitanism and multi-ethnicity, Insilico hires the best people from the best of the colleges with no prejudice. Ensuring meaningfulness and psychological safety to all its employees and enabling them to engage all their energies, physical, cognitive and emotional, at work, Insilico assures to address any quality and stability concern of its clients – engaged and happy employees perform better, stay longer and keep clients satisfied.

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Published Date : 27/06/2018

Location

:

Bangalore/Hyderabad

Professional Experience

:

3+ years

No. of Vacancies

:

35

Job Profile

:
  • 2+ Years of India Experience with strong back ground in ASIC Physical Design: Floor planning, P&R, Extraction, IR Drop Analysis, Static Timing and Signal Integrity.
  • Exposure to advance Technology: 28nm, 40nm, 45nm, 65nm
  • Hands on experience in cadence or Synopsys tool (Encounter, ICC, PT/PTSI, TEMPUS, DC, RC, VOLTAS)

Published Date : 27/06/2018

Location

:

Bangalore

Professional Experience

:

3+ years

No. of Vacancies

:

40

Job Profile

:
  • 3+ years of experience in IP / SoC / core CPU level Verification.
  • Good experience in functional verification
  • Good experience in System Verilog & UVM or Assembly language or SystemC or C based testcase development.
  • Having experience in GLS, Low power verification or Power management domain (UPF) is preferred not mandatory
  • Any protocol expertise like Ethernet, PCIe, DDR & USB is a added advantage to have

Published Date : 27/06/2018

Location

:

Bangalore/Hyderabad

Professional Experience

:

3+ years

No. of Vacancies

:

30

Job Profile

:
  • Layout of Analog, Mixed-Signal or RF circuit blocks such as amplifiers, LDOs, comparators, ADC, DAC, PLL, filters etc in deep sub-micron processes (28nm, 22nm, 16nm, 14nm, 10nm, 7nm etc).
  • Block level floor planning and trade-off analysis.
  • Review and update layout for quality including signal integrity, power distribution, and parasitics.
  • Layout of sensitive active/passive components including resistors, capacitors, and inductors.
  • Design verification including DRC, LVS, ERC and Antenna, EMIR and RC extraction.

Published Date : 27/06/2018

Location

:

Bangalore/Hyderabad

Professional Experience

:

2+ years

No. of Vacancies

:

10

Job Profile

:
  • Over 2+ Years of experience with Scan insertion & ATPG using Fastscan / TestKompress / DFTCompiler / DFTMax / DFTAdvisor / TetraMax.
  • Pattern Simulation with and without timing annotation & debugging

Published Date : 27/06/2018

Location

:

Bangalore

Professional Experience

:

3+ years

No. of Vacancies

:

10

Job Profile

:
  • Should be very strong in Synthesis & Timing concepts
  • Should have knowledge of DC-topo, RTL Compiler or talus
  • Should have handled both block and top level.
  • Should have done both pre and post layout STA.

Published Date : 27/06/2018

Location

:

Santa Clara, CA

Professional Experience

:

5+ years

No. of Vacancies

:

2

Job Profile

:
  • DFT/DFD/DFM techniques for complex SoCs
  • Fault modeling Stuck-at, Transition, Path Delay, IDDQ, and other models
  • Scan Insertion, ATPG, Scan Compression, At-speed Testing
  • Scan Insertion using DFTCompiler or equivalent
  • Exposure to industry standard ATPG tools like Mentor TestKompress, Synopsys TetraMax, Cadence Encounter Test
  • Industry standard simulation tools such as VCS, Questasim, NCVerilog -Scripting in Perl and Tcl
  • Exposure to SoC design and test for mobile market applications

Published Date : 27/06/2018

Location

:

Santa Clara, CA, Austin, TX

Professional Experience

:

3+ years

No. of Vacancies

:

5

Job Profile

:
  • 2+ years of hardware verification experience.
  • Good Knowledge of high performance microprocessor architecture.
  • Understanding of verification methodology.
  • Development experience in languages common to the industry (e.g., Verilog, SystemVerilog, C, C++, Perl, Python).
  • Self-motivated, team player, with good communication skills.

Published Date : 27/06/2018

Location

:

Santa Clara, CA/Austin, TX/Boxborough, MA

Professional Experience

:

5+ years

No. of Vacancies

:

5

Job Profile

:
  • Experience in ASIC/IP functional Verification
  • Strong expertise in Ethernet Mac Layer Verification
  • Experience developing UVM, System Verilog components from Scratch
  • Good experience in developing test plan covering protocol features
  • Sound debugging skills
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